Graphics-intensive applications executed by a processor-based device, such as a computer, are becoming increasingly pervasive. Such applications include computer-aided design (CAD) applications, video games, imaging applications, and the like. A number of these applications operate in real-time, requiring the processing device to render the graphics at very fast speeds. As consumers and programmers continually demand greater graphics complexity in their applications, the devices rendering the graphics must continually improve as well.
The processor-based device may rely, at least in part, on a graphics (i.e., video) card for displaying graphics on a display device, such as a monitor. A graphics card typically includes one or more dedicated graphics processors, which are optimized for graphics rendering. A graphics card typically also includes one or more dedicated memories, such as a synchronous graphics random access memory (SGRAM), which are essentially a specialized synchronous dynamic random access memory (SDRAM) for use on graphics cards.
A continuing challenge for memory designers is increasing performance, that is, the speed at which data is transferred to and from memory. Double data rate dynamic random access memory (DDR DRAM) increases performance by providing for two data accesses within a single clock cycle, that is, by enabling the memory to read data on both the rising and falling edges of each clock cycle. This essential concept of the DDR DRAM has been extended to SDRAMs and SGRAMs, resulting in DDR SDRAM and DDR SGRAM.
A number of graphics cards utilize graphics double data rate (GDDR) SGRAM. The Joint Electron Devices Engineering Council (JEDEC) maintains, inter alia, a GDDR4 SGRAM specification, which defines a minimum set of requirements for JEDEC-standard-compatible GDDR4 SGRAM devices. For illustrative purposes only, we refer to Ballot Template Version draft rev. G of the GDDR4 SGRAM specification (hereinafter “GDDR4 SGRAM specification”), the disclosure of which is incorporated herein by reference.
The GDDR4 SGRAM specification defines the use of two uni-directional data strobe signals: a read data strobe signal (RDQS) and a write data strobe signal (WDQS). The RDQS is a data strobe transmitted by the GDDR4 SGRAM during READs, and is edge-aligned with data for READs. The WDQS is a data strobe sent by a memory controller during WRITEs, and is center-aligned with data for WRITEs.
During a write access, the first valid data-in element is registered on the rising edge of the WDQS following the write latency (WL), which is programmable via the mode register (MR). Subsequent data elements are registered on successive edges of the WDQS. According to the GDDR4 SGRAM specification, the WL may be set from one to seven clock cycles.
The time between the WRITE command (i.e., at the rising edge of the external clock (CLK)) and the first valid edge of WDQS is referred to as the TDQSS. According to the GDDR4 SGRAM specification, the TDQSS is specified relative to the WL between (WL−0.25CLK) and (WL+0.25CLK).
A proposed graphics standard known as GDDR5 SGRAM defines the TDQSS by a specific range, −500 to +500 picoseconds (ps), from the CLK. This presents a potential problem at higher operating frequencies not present with GDDR4 SGRAM. For example, at an operating frequency of 1.25 GHz, the tolerance of −500 ps to +500 ps results in more than one-half clock cycle in each direction. By having a tolerance greater than one-half clock cycle in either direction, distinguishing between a very early phase (i.e., more than one-half clock cycle) versus a slightly late phase (i.e., less than one clock cycle) or between a very late phase (i.e., more than one clock cycle) versus a slightly early phase (i.e., less than one clock cycle) becomes difficult.
For these and other reasons, there is a need for the present invention.